ROM memory circuits are widely used in electronic devices. FIG. 1 is an electrical schematic of a conventional ROM circuit 100. It includes sense amplifier 102, precharge transistors 114, multiplexers (MUX) 112a and 112b, sense terminals SA 116 and SAB 118, a plurality of bit lines 108, and one or more reference bit lines 110.
Each of bit lines 108 is electrically connected to one or a plurality of memory cells (not shown in FIG. 1) of ROM circuit 100. Each MUX 112a or 112b includes a plurality of transistors (not shown in FIG. 1). Each transistor in MUX 112a is electrically connected to one of bit lines 108, and each transistor in MUX 112b is electrically connected to one of reference bit lines 110. Sense amplifier 102 includes a sense terminal SA 116 and an optional sense terminal SAB 118. Each of precharge transistors 114 is electrically connected to one of sense terminals SA 116 and SAB 118 and to Vdd 120 (power supply voltage).
Precharge transistors 114 are configured to precharge sense terminals SA 116 and SAB 118 to Vdd prior to an operation of reading digital data from the memory cells of ROM circuit 100. Each transistor in MUX is electrically connected to one of bit lines 108 or one of reference bit lines 110 in a manner that provides for MUX 112a or 112b to select each of bit lines 108 or reference bit lines 110 as input to MUX 112a or 112b. Particularly, MUX 112a selects one bit line from a plurality of bit lines 108 as input to sense amplifier 102 through sense terminal SA 116 and MUX 112b selects one reference bit line from a plurality of reference bit lines 110 as input to sense amplifier 102 through sense terminal SAB 118. Sense amplifier 102 is configured to sense the electrical state (e.g., the voltage state) of sense terminals SA 116 and SAB 118.
Typically, during the operation of conventional ROM circuits, such as ROM circuit 100 illustrated in FIG. 1, all sense terminals, more particularly, sense terminals SA 116 and SAB 118 as shown in FIG. 1, are precharged to Vdd 120 by precharge transistors 114 to a READ operation. If the digital data to be read from a bit line (e.g. bit line 108a as shown in FIG. 1) selected by MUX 112a is a digital 0, then bit line 108a will have been discharged to ground (i.e., a digital 0 or a “low” state) through a memory cell subsequent to its having been precharged. On the other hand, if the digital data to be read from bit line 108a selected by MUX 112a is a digital 1, then bit line 108a will be in a high impedance state (i.e., a digital 1 or a “high” state). The discharged to ground or high impedance state of bit line 108a is sensed and amplified by sense amplifier 102. However, during read operations, bit line 108a is always over-discharged because of the leakage of memory cells. Tuning between read 1 signal and read 0 signal is dependent on the discharging level of bit line 108a. In order to have a correct swing value for sensing, bit line 108a has to be discharged to an intermediate voltage. The intermediate voltage, however, may be lower than the threshold value of the transistors in MUX. This limits the signal developed on sense terminal SA 116. The performance of ROM 100 is therefore slowed down by this limiting factor.
In order to counter leakage, keepers may be used. As shown in FIG. 2a, ROM circuit 200 includes sense amplifier 202, precharge transistor 214, multiplexer (MUX) 212, sense terminals SA 216 and SAB-Ref 218, bit lines 208. Further, each bit line of bit lines 208 connects to a keeper 230.
Each bit line of bit lines 208 is electrically connected to one or a plurality of memory cells (not shown in FIG. 2a) of ROM circuit 200. MUX 212 includes a plurality of transistors (not shown in FIG. 2). Each transistor in MUX 212 is electrically connected to one of bit lines 208. Sense amplifier 202 includes a sense terminal SA 216 and an optional sense terminal SAB-Ref 218. Precharge transistor 214 is electrically connected to sense terminal SA 216 and to Vdd 220 (power supply voltage).
Precharge transistor 214 is configured to precharge sense terminal SA 216 to Vdd according to a control signal PrechSig 250. Each transistor in MUX 212 is electrically connected to one of bit lines 208 in a manner that provides for MUX 212 to select each of bit lines 208 as input to MUX 212. For example, MUX 212 selects one bit line 208a from a plurality of bit lines 208 as input to sense amplifier 202 through SA 216. Sense amplifier 202 is configured to sense the electrical state (e.g., the voltage state) of sense terminal SA 216.
Further, each bit line of bit lines 208 connects to a keeper. One exemplary keeper 230 is shown in detail in FIG. 2b. Typically, keeper 230 is a conventional feedback keeper using an inverter 222 and a keeper transistor 224 to hold the output high. Source terminal of keeper transistor 224 and input of inverter 222 are coupled to a bit line (for example, bit line 208a), and gate of keeper transistor 224 is driven by the output of inverter 222. In other words, keeper 230 is controlled by bit line inverted command to keep voltage of bit line 208a higher than the voltage threshold of inverter 222. During read operation, bit line 208a is less discharged due to the implementation of keepers 230. However, as the voltage of bit line 208a decreases to the threshold voltage Vth of keeper transistor 224, keeper 230 is turned off. As keeper 230 is turned off, the voltage of bit line 208a begins to drop dramatically, and the sensing windows may be unstable.
Referring to FIG. 2c, reading operation of ROM circuit 200 will be described. First, at time t21, precharge signal 250 is switched from Low to High, and a precharge period is terminated. The voltage in precharged bit line 208a begins discharging rapidly due to leakage. Keeper 230 is in active status to stabilize (or keep) the voltage in bit line 208a against leakage. At time t22, the voltage of bit line 208a drops to the threshold voltage value Vth of keeper transistor 224. Keeper 230 is switched off as a result. As keeper 230 is off, the voltage of bit line BL begins to drop dramatically due to leakage in the absence of keeper 230. Next, at time t23, when the voltage of BL almost drops to ground, sense amplifier is switched on, and moves to a sense period. Next, at time t24, after sensing, precharge signal 250 is switched from High to Low, so that bit line 208a is again charged to power supply potential Vdd.
The drop in voltage on bit line 208a in time period between t22 and t23 leads to several disadvantages including an unstable sensing window. A feedback-controlled keeper only partly resolves this problem, while introducing others, potentially complicating sensing.
Therefore, a keeper circuit that reliably stabilizes voltage in a memory without interfering with sensing process will be desirable. Also, it would be preferable for such a keeper circuit to occupy less space in the ROM circuit.